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FEATURES Total I DD: 7.1 mA Bandwidth/RF 3.0 GHz ADF4217L/ADF4218L, IF 1.1 GHz ADF4219L, IF 1.0 GHz 2.6 V to 3.3 V Power Supply 1.8 V Logic Compatibility Separate V P Allows Extended Tuning Voltage Selectable Dual Modulus Prescaler Selectable Charge Pump Currents Charge Pump Current Matching of 1% 3-Wire Serial Interface Power-Down Mode APPLICATIONS Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA) Base Stations for Wireless Radio (GSM, PCS, DCS, WCDMA) Wireless LANS Communications Test Equipment Cable TV Tuners (CATV)
Dual Low Power Frequency Synthesizers ADF4217L/ADF4218L/ADF4219L
GENERAL DESCRIPTION
The ADF4217L/ADF4218L/ADF4219L are low power dual frequency synthesizers that can be used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. They can provide the LO for both the RF and IF sections. They consist of a low noise digital PFD (Phase Frequency Detector), a precision charge pump, a programmable reference divider, programmable A and B counters, and a dual-modulus prescaler (P/P + 1). The A and B counters, in conjunction with the dual modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R Counter) allows selectable REFIN frequencies at the PFD input. A complete PLL (Phase-Locked Loop) can be implemented if the synthesizers are used with an external loop filter and VCOs (Voltage Controlled Oscillators). Control of all the on-chip registers is via a simple 3-wire interface with 1.8 V compatibility. The devices operate with a power supply ranging from 2.6 V to 3.3 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
ADF4219L ONLY NC VDD1 VDD2 VP1 VP2
N = BP + A 11(13)-BIT IF B COUNTER IFINA IFINB ADF4217L ADF4218L ONLY REFIN IF PRESCALER 6(5)-BIT IF A COUNTER IF LOCK DETECT 14(15)-BIT IF R COUNTER CLOCK DATA LE 22-BIT DATA SDOUT REGISTER 14(15)-BIT RF R COUNTER RF LOCK DETECT PHASE COMPARATOR
ADF4217L/ ADF4218L/ ADF4219L
CHARGE PUMP CPIF
BUFFER
OUTPUT MUX
MUXOUT
N = BP + A 11(13)-BIT RF B COUNTER RFINA RFINB RF PRESCALER 6(5)-BIT RF A COUNTER PHASE COMPARATOR
CHARGE PUMP
CPRF
FEATURES IN ( ) REFER TO ADF4219L NC = NO CONNECT
DGNDRF
AGNDRF
DGNDIF
AGNDIF
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
ADF4217L/ADF4218L/ADF4219L-SPECIFICATIONS1
(VDD1 = VDD2 = 2.6 V to 3.3 V; VP1, VP2 = VDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted.)
BChips2 (Typical) Parameter RF CHARACTERISTICS RF Input Frequency (RFIN) ADF4217L, ADF4218L ADF4217L, ADF4218L ADF4219L RF Input Sensitivity ADF4217L, ADF4218L ADF4219L IF Input Frequency (IFIN) ADF4217L/ADF4218L ADF4219L P = 16/17 ADF4219L P = 8/9 IF Input Sensitivity Maximum Allowable Prescaler Output Frequency3 REFIN CHARACTERISTICS Reference Input Frequency Reference Input Sensitivity REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency4 CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy ICP Three-State Leakage Current Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance Reference Input Current LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage POWER SUPPLIES VDD1 VDD2 VP1, VP2 IDD (RF + IF)5 (RF only)5 (IF only)5 IP(IP1 + IP2) Low Power Sleep Mode B Version
1
Unit
Test Conditions/Comments Use a square wave for operation below minimum frequency spec.
0.1/3.0 0.1/2.5 0.8/2.2 -15/0 -20/0 0.045/1.1 0.045/1.0 0.045/0.55 -15/0 188 10/110 0.5 10 100 56
0.1/3.0 0.1/2.5 0.8/2.2 -15/0 -20/0 0.045/1.1 0.045/1.0 0.045/0.55 -15/0 188 10/110 0.5 10 100 56
GHz min/max GHz min/max GHz min/max dBm min/max dBm min/max GHz min/max GHz min/max GHz min/max dBm min/max MHz max MHz min/max V p-p min pF max mA max MHz max
-10 dBm minimum input signal -15 dBm minimum input signal -20 dBm minimum input signal
-15 dBm minimum input signal -10 dBm minimum input signal -10 dBm minimum input signal
For f < 10 MHz, use dc-coupled square wave, (0 to VDD). AC-Coupled. When dc-coupled: 0 to VDD max. (CMOS compatible)
4 1 1 1 6 5 2 1.4 0.6 1 10 100 VDD - 0.4 0.4 2.6/3.3 VDD1 VDD1/5.5 V 10 7 5 0.6 1
4 1 1 1 6 5 2 1.4 0.6 1 10 100 VDD - 0.4 0.4 2.6/3.3 VDD1 VDD1/5.5 V 10 7 5 0.6 1
mA typ mA typ % typ nA typ % max % max % typ V min V max mA max pF max mA max V min V max V min/V max V min/V max mA max mA mA mA typ mA typ
0.5 V < VCP < VP - 0.5, 1% typ 0.5 V < VCP < VP - 0.5, 0.1% typ VCP = VP/2
IOH = 1 mA IOL = 1 mA
7.1 mA typical 4.7 mA typical 3.4 mA typical TA = 25C
-2-
REV. B
ADF4217L/ADF4218L/ADF4219L
Parameter NOISE CHARACTERISTICS RF Phase Noise Floor7 IF Phase Noise Floor7 Phase Noise Performance8 RF9 RF10 IF11 IF12 Spurious Signals RF9 RF10 IF11 IF12
6
B Version -171 -163 -167 -159 -75 -90 -77 -86 -78/-85 -80/-84 -79/-86 -80/-84
1
BChips2 (Typical) -171 -163 -167 -159 -75 -90 -77 -86 -78/-85 -80/-84 -79/-86 -80/-84
Unit dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc typ dBc typ dBc typ dBc typ
Test Conditions/Comments @ 30 kHz PFD Frequency @ 200 kHz PFD Frequency @ 30 kHz PFD Frequency @ 200 kHz PFD Frequency @ VCO Output 1.95 GHz Output; 30 kHz PFD 900 MHz Output; 200 kHz PFD 900 MHz Output; 30 kHz PFD 900 MHz Output; 200 kHz PFD Measured at Offset of fPFD/2fPFD
NOTES 1 Operating temperature range is as follows: B Version: -40C to +85C. 2 The BChip specifications are given as typical values. 3 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that is less than this value. 4 Guaranteed by design. Sample tested to ensure compliance. 5 This includes relevant I P. 6 VDD = 3 V; P = 16/32; IFIN /RFIN for ADF4218L, ADF4219L = 540 MHz/900 MHz. 7 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value). 8 The phase noise is measured with the EVAL-ADF421xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer. (fREFOUT = 10 MHz @ 0 dBm) 9 fREFIN = 10 MHz; f PFD = 30 kHz; Offset frequency = 1 kHz; f RF = 1.95 GHz; N = 65000; Loop B/W = 3 kHz 10 fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; f RF = 900 MHz; N = 4500; Loop B/W = 20 kHz 11 fREFIN = 10 MHz; f PFD = 30 kHz; Offset frequency = 1 kHz; f IF = 900 MHz; N = 30000; Loop B/W = 3 kHz 12 fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; f IF = 900 MHz; N = 4500; Loop B/W = 20 kHz Specifications subject to change without notice.
TIMING CHARACTERISTICS
Limit at TMIN to TMAX (B Version) 10 10 25 25 10 50
(VDD1 = VDD2 = 3 V 10%, 5 V 10%; VDD1, VDD2 VP1, VP2 6.0 V ; AGNDRF1 = DGNDRF1 = AGNDRF2 = DGNDRF2 = 0 V; TA = TMIN to TMAX, unless otherwise noted.)
Parameter t1 t2 t3 t4 t5 t6
Unit ns min ns min ns min ns min ns min ns min
Test Conditions/Comments DATA to CLOCK Setup Time DATA to CLOCK Hold Time CLOCK High Duration CLOCK Low Duration CLOCK to LE Setup Time LE Pulsewidth
Guaranteed by design but not production tested.
t3
CLOCK
t4
t1
DATA DB21 (MSB) DB20
t2
DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1)
t6
LE
t5
LE
Figure 1. Timing Diagram
REV. B
-3-
ADF4217L/ADF4218L/ADF4219L
ABSOLUTE MAXIMUM RATINGS 1, 2
(TA = 25C, unless otherwise noted.) VDD1 to GND3 . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +3.6 V VDD1 to VDD2 . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +0.3 V VP1, VP2 to GND . . . . . . . . . . . . . . . . . . . . -0.3 V to +5.8 V VP1, VP2 to VDD1 . . . . . . . . . . . . . . . . . . . . -0.3 V to +5.5 V Digital I/O Voltage to GND . . . . . . . . -0.3 V to VDD + 0.3 V Analog I/O Voltage to GND . . . . . . . . . -0.3 V to VP + 0.3 V REFIN, RF1IN (A, B), IFIN (A, B) to GND . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V RFINA to RFINB . . . . . . . . . . . . . . . . . . . . . . . . . . 320 mV Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Maximum Junction Temperature . . . . . . . . . . . . . . . . 150C
TSSOP JA Thermal Impedance . . . . . . . . . . . . . 150.4C/W CSP JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112C/W Lead Temperature, Soldering TSSOP, Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . 215C TSSOP, Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . 220C CSP, Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . 240C CSP, Infrared (20 sec) . . . . . . . . . . . . . . . . . . . . . . . 240C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 This device is a high performance RF integrated circuit with an ESD rating of < 2 kV, and is ESD sensitive. Proper precautions should be taken for handling and assembly. 3 GND = AGND = DGND = 0 V
ORDERING GUIDE
Model ADF4217L/ADF4218L/ADF4219LBRU ADF4217L/ADF4218L/ADF4219LBCC
*Contact the factory for chip availability.
Temperature Range -40C to +85C -40C to +85C
Package Description Thin Shrink Small Outline Package (TSSOP) Chip Scale Package CASON (CSP)
Package Option* RU-20 CC-24
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADF4217L/ ADF4218L/ADF4219L features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
REV. B
ADF4217L/ADF4218L/ADF4219L
PIN CONFIGURATIONS TSSOP
VDD1 VP1 CPRF DGNDRF RFINA RFINB AGNDRF REFIN DGNDIF MUXOUT
1 2 3 4 5 6 7 8 9 10 20 19 18 17
TSSOP
VDD2 VP2 CPIF DGNDIF IFINA IFINB AGNDIF LE DATA CLK
VDD1 VP1 CPRF DGNDRF RFINA RFINB AGNDRF REFIN DGNDIF MUXOUT
1 2 3 4 5 6 7 8 9 10 20 19 18 17
VDD2 VP2 CPIF DGNDIF IFIN AGNDIF NC LE DATA CLK
ADF4217L/ ADF4218L
16 15 14 13 12 11
ADF4219L
16 15 14 13 12 11
NC = NO CONNECT
CHIP SCALE
VDD1 VDD2 VP2
CHIP SCALE
VDD1 VDD2
23
24
23
22 21 20 19
NC VP1 CPRF DGNDRF RFINA RFINB AGNDRF REFIN NC
1 2 3 4 5 6 7 8 9 10 11 12
NC CPIF DGNDIF IFINA IFINB AGNDIF LE DATA NC
NC VP1 CPRF DGNDRF RFINA RFINB AGNDRF REFIN NC
24 1 2 3 4 5 6 7 8 9 10
VP2
22 21 20 19 18
NC CPIF DGNDIF IFIN AGNDIF NC LE DATA NC
ADF4217L/ ADF4218L
18 17 16 15 14 13
ADF4219L
17 16 15 14 13
11
12
MUXOUT
DGNDIF
MUXOUT
DGNDIF
CLK
NC = NO INTERNAL CONNECT
NC = NO INTERNAL CONNECT
REV. B
-5-
CLK
ADF4217L/ADF4218L/ADF4219L
PIN FUNCTION DESCRIPTIONS
Mnemonic VDD1
Function Positive Power Supply for the RF Section. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. VDD1 should have a value of between 2.6 V and 3.3 V. VDD1 must have the same potential as VDD2. Power Supply for the RF Charge Pump. This should be greater than or equal to VDD. Output from the RF Charge Pump. When enabled, this provides ICP to the external loop filter, which in turn drives the external VCO. Ground Pin for the RF Digital Circuitry Input to the RF Prescaler. This low-level input signal is normally ac-coupled to the external VCO. Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a small bypass capacitor, typically 100 pF. Ground Pin for the RF Analog Circuitry Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance of 100 kW This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled. Ground Pin for the IF Digital, Interface, and Control Circuitry This multiplexer output allows either the IF/RF Lock Detect, the scaled RF, or the scaled Reference Frequency to be accessed externally. See Table V. Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 22-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high impedance CMOS input. Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches, the latch being selected using the control bits. Ground Pin for the IF Analog Circuitry This pin is not connected internally (ADF4219L only). Complementary Input to the IF Prescaler. This point should be decoupled to the ground plane with a small bypass capacitor, typically 100 pF (ADF4217L/ADF4218L only). Input to the IF Prescaler. This low-level input signal is normally ac-coupled to the external VCO. Ground Pin for the IF Digital, Interface, and Control Circuitry. Output from the IF Charge Pump. When enabled, this provides ICP to the external loop filter, which in turn drives the external VCO. Power Supply for the IF Charge Pump. This should be greater than or equal to VDD. Positive Power Supply for the IF Interface and Oscillator Sections. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. VDD2 should have a value of between 2.6 V and 3.3 V. VDD2 must have the same potential as VDD1.
V P1 CPRF DGNDRF RFINA RFINB AGNDRF REFIN DGNDIF MUXOUT CLK DATA LE AGNDIF NC IFINB IFINA DGNDIF CPIF V P2 VDD2
-6-
REV. B
Typical Performance Characteristics-ADF4217L/ADF4218L/ADF4219L
0 -5 VDD = 3V VP = 3V
0 -10 -20 REFERENCE LEVEL = -11.2dBm VDD = 3V, VP = 5V ICP = 4mA PFD FREQUENCY = 200kHz RES BANDWIDTH = 1kHz VIDEO BANDWIDTH = 1kHz SWEEP = 2.5 SECONDS AVERAGES = 10
RF INPUT POWER - dBm
OUTPUT POWER - dB
-10 -15 -20 -25 TA = 25 C -30
-30 -40 -50 -60
-78dBc -70 -80
-35 -40 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 RF INPUT FREQUENCY - GHz
-90 -100 -400kHz -200kHz 1960MHz FREQUENCY 200kHz 400kHz
TPC 1. Input Sensitivity, RF Input
TPC 4. Reference Spurs, RF Side (1960 MHz, 200 kHz, 20 kHz)
0 -5 -10 -15 -20 -25 -30 -35 -40 0.1 0.6 1.1 IF INPUT FREQUENCY - GHz 1.6 VDD = 3V VP = 3V
10dB/DIVISION -40 -50 -60
RL = -40dBc/Hz
rms NOISE = 1.2
IF INPUT POWER - dBm
PHASE NOISE - dBc/Hz
1.2 rms -70 -80 -90 -100 -110 -120 -130 -140 100Hz
FREQUENCY OFFSET FROM 1960MHz CARRIER
1MHz
TPC 2. Input Sensitivity, IF Input
TPC 5. Integrated Phase Noise, RF Side (1960 MHz, 200 kHz, 20 kHz)
0 -10 -20 REFERENCE LEVEL = -11.2dBm VDD = 3V, VP = 5V ICP = 4.0mA PFD FREQUENCY = 200kHz RES. BANDWIDTH = 10Hz VIDEO BANDWIDTH = 10Hz SWEEP = 1.9 SECONDS AVERAGES = 20
0 -10 -20
OUTPUT POWER - dB
REFERENCE LEVEL = -4.2dBm
OUTPUT POWER - dB
-30 -40 -50 -60 -70 -80 -90
-30 -40 -50 -60 -70 -80 -90
VDD = 3V, VP = 5V ICP = 4mA PFD FREQUENCY = 200kHz RES BANDWIDTH = 10Hz VIDEO BANDWIDTH = 10Hz SWEEP = 1.9 SECONDS AVERAGES = 20
-83dBc/Hz
-87dBc/Hz
-100
-100
-2kHz -1kHz 900MHz FREQUENCY 1kHz 2kHz
-2kHz
-1kHz
900MHz FREQUENCY
1kHz
2kHz
TPC 3. Phase Noise, RF Side (1960 MHz, 200 kHz, 20 kHz)
TPC 6. Phase Noise, IF Side (900 MHz, 200 kHz, 20 kHz)
REV. B
-7-
ADF4217L/ADF4218L/ADF4219L
0 -10 -20
REFERENCE LEVEL = -4.2dBm
-120 VDD = 3V, VP = 5V ICP = 4.0mA PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 20kHz RES. BANDWIDTH = 10kHz VIDEO BANDWIDTH = 10kHz SWEEP = 1.9 SECONDS AVERAGES = 20 VDD = 3V VP = 5V -130
-30 -40 -50 -60 -70 -80 -90
PHASE NOISE - dBc/Hz
OUTPUT POWER - dB
-140
-150
-160
-83dBc
-170
-100
-400kHz
-200kHz
900MHz FREQUENCY
200kHz
400kHz
-180
1
10 100 1000 PHASE DETECTOR FREQUENCY - kHz
10000
TPC 7. Reference Spurs, IF Side (900 MHz, 200 kHz, 20 kHz)
TPC 10. Phase Noise Referred to CP Output vs. PFD Frequency, IF Side
10dB/DIVISION -40 -50 -60
PHASE NOISE - dBc/Hz
RL = -50dBc/Hz
rms NOISE = 0.9
-60 VDD = 3V VP = 5V -70
-70 -80 -90 -100 -110 -120 -130 -140 100Hz
PHASE NOISE - dBc/Hz
-80
-90
FREQUENCY OFFSET FROM 1750MHz CARRIER
1MHz
-100 -40
-20
0
20 40 TEMPERATURE - C
60
80
100
TPC 8. Integrated Phase Noise, IF Side (900 MHz, 200 kHz, 20 kHz)
TPC 11. Phase Noise vs. Temperature, RF Side (1960 MHz, 200 kHz, and 20 kHz)
-120 VDD = 3V VP = 5V -130
-60 VDD = 3V VP = 5V -70
PHASE NOISE - dBc/Hz
-140
-150
PHASE NOISE - dBc/Hz
1 10 100 1000 PHASE DETECTOR FREQUENCY - kHz 10000
-80
-160
-90
-170
-180
-100 -40
-20
0
20 40 TEMPERATURE - C
60
80
100
TPC 9. Phase Noise Referred to CP Output vs. PFD Frequency, RF Side
TPC 12. Phase Noise vs. Temperature, IF Side (900 MHz, 200 kHz, and 20 kHz)
-8-
REV. B
ADF4217L/ADF4218L/ADF4219L
6 VP = 5V ICP = 4mA 4
2
ICP - mA
0
-2
-4
-6 0 0.5 1.0 1.5 2.0 2.5 3.0 VCP - V 3.5 4.0 4.5 5.0
TPC 13. Charge Pump Output Characteristics
CIRCUIT DESCRIPTION Reference Input Section
Prescaler
The Reference Input stage is shown in Figure 2. SW1 and SW2 are normally-closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down.
POWER-DOWN CONTROL
The dual modulus prescaler (P/P + 1), along with the A and B counters, enables the large division ratio, N, to be realized (N = BP + A). This prescaler, operating at CML levels, takes the clock from the IF/RF input stage and divides it down to a manageable frequency for the CMOS A and B counters. It is based on a synchronous 4/5 core. The prescaler is selectable. On the IF side, it can be set to either 8/9 (DB20 of the IF AB Counter Latch set to 0) or 16/17 (DB20 set to 1). On the RF side of the ADF4217L/ADF4218L, it can be set to 64/65 or 32/33. On the ADF4219L, the RF prescaler can be set to 16/17 or 32/33. See Tables V, VI, VIII, and IX.
NC SW2 REFIN NC SW1 SW3 NO
50k
BUFFER
TO R COUNTER
A AND B COUNTERS
NC = NORMALLY CLOSED NO = NORMALLY OPEN
Figure 2. Reference Input Stage
IF/RF Input Stage
The A and B CMOS counters combine with the dual modulus prescaler to allow a wide ranging division ratio in the PLL feedback counter. The devices are guaranteed to work when the prescaler output is 188 MHz or less. Typically they will work with 250 MHz output from the prescaler.
The IF/RF input stage is shown in Figure 3. It is followed by a two-stage limiting amplifier to generate the CML clock levels needed for the prescaler.
BIAS GENERATOR 500 1.6V AVDD 500
FROM IF/RF INPUT STAGE
N = BP + A 11(13)-BIT B COUNTER LOAD PRESCALER P/P+1 MODULUS CONTROL LOAD 6(5)-BIT A COUNTER TO PFD
RFINA
RFINB
Figure 4. Reference Input Stage. A and B Counters
AGND
Figure 3. IF/RF Input Stage
REV. B
-9-
ADF4217L/ADF4218L/ADF4219L
The A and B counters, in conjunction with the dual modulus prescaler, make it possible to generate output frequencies that are spaced only by the Reference Frequency divided by R. The equation for the VCO frequency is as follows:
MUXOUT AND LOCK DETECT
fVCO = (P B ) + A fREFIN / R
fVCO = Output frequency of external voltage controlled oscillator (VCO). P B A = Preset modulus of dual modulus prescaler (8/9, 16/17, and so on). = Preset Divide Ratio of binary 11-bit counter (ADF4217L/ ADF4218L), binary 13-bit counter (ADF4219L). = Preset Divide Ratio of binary 6-bit A counter (ADF4217L/ ADF4218L), binary 5-bit counter (ADF4219L).
[
]
The output multiplexer on the ADF4217L family allows the user to access various internal points on the chip. The state of MUXOUT is controlled by P3, P4, P11, and P12. See Tables IV and VII. Figure 6 shows the MUXOUT section in block diagram form.
DVDD
IF ANALOG LOCK DETECT IF R COUNTER OUTPUT IF N COUNTER OUTPUT IF/RF ANALOG LOCK DETECT RF R COUNTER OUTPUT RF N COUNTER OUTPUT RF ANALOG LOCK DETECT MUX CONTROL MUXOUT
fREFIN = Output frequency of the external reference frequency oscillator. R = Preset divide ratio of binary 14-bit programmable reference counter (1 to 16383). The ADF4219L has an R divide of 15 bits.
Lock Detect R COUNTER
DGND
Figure 6. MUXOUT Circuit
The 14-bit R counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to 16,383 are allowed. The extra R15 bit on the ADF4219L allows ratios from 1 to 32767.
PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP
MUXOUT can be programmed for analog lock detect. The N-channel open-drain analog lock detect should be operated with an external pull-up resistor of 10 kW nominal. When lock has been detected, it is high with narrow low-going pulses.
INPUT SHIFT REGISTER
The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them. Figure 5 is a simplified schematic.
VP UP CHARGE PUMP
HI
D1 U1
Q1
R DIVIDER
CLR1
The functional block diagram for the ADF4217L family is shown on page 1. The main blocks include a 22-bit input shift register, a 14-bit R counter, and an N counter. The N counter is comprised of a 6-bit A counter and an 11-bit B counter for the ADF4217L and the ADF4218L. The 18-bit N counter on the ADF4219L is comprised of a 13-bit B counter and a 5-bit A counter. Data is clocked into the 22-bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of four latches on the rising edge of LE. The destination latch is determined by the state of the two control bits (C2, C1) in the shift register. These are the two LSBs, DB1 and DB0 as shown in the timing diagram of Figure 1. The truth table for these bits is shown in Table I.
Table I. C2, C1 Truth Table
DELAY ELEMENT
U3
CP
Control Bits C2 C1
HI N DIVIDER CLR2 DOWN D2 Q2 U2 CPGND
Data Latch IF R Counter IF AB Counter (and Prescaler Select) RF R Counter RF AB Counter (and Prescaler Select)
0 0 1 1
0 1 0 1
R DIVIDER
N DIVIDER
CP OUTPUT
Figure 5. PFD Simplified Schematic
-10-
REV. B
ADF4217L/ADF4218L/ADF4219L
Table II. ADF4217L/ADF4218L Family Latch Summary
IF REFERENCE COUNTER LATCH
THREE-STATE CPIF IF PD POLARITY IF LOCK DETECT
NOT USED
IF CP GAIN
IF FO
14-BIT REFERENCE COUNTER, R
CONTROL BITS
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P4 P3 P2 P5 P1 R14 R13 R12 R11 R10 R9
DB9 R8
DB8 R7
DB7 R6
DB6 R5
DB5 R4
DB4 R3
DB3 R2
DB2 R1
DB1
DB0
C2 (0) C1 (0)
IF AB COUNTER LATCH
IF POWER-DOWN IF PRESCALER
11-BIT B COUNTER
NOT USED
6-BIT A COUNTER
CONTROL BITS
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P7 P6 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2
DB9 B1
DB8
DB7 A6
DB6 A5
DB5 A4
DB4 A3
DB3 A2
DB2 A1
DB1
DB0
C2 (0) C1 (1)
RF REFERENCE COUNTER LATCH
THREE-STATE CPIF RF PD POLARITY RF LOCK DETECT RF CP GAIN
RF FO
NOT USED
14-BIT REFERENCE COUNTER, R
CONTROL BITS
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P12 P11 P10 P13 P9 R14 R13 R12 R11 R10 R9
DB9 R8
DB8 R7
DB7 R6
DB6 R5
DB5 R4
DB4 R3
DB3 R2
DB2 R1
DB1
DB0
C2 (1) C1 (0)
RF AB COUNTER LATCH
RF POWER-DOWN RF PRESCALER
11-BIT B COUNTER
NOT USED
6-BIT A COUNTER
CONTROL BITS
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P16 P14 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2
DB9 B1
DB8
DB7 A6
DB6 A5
DB5 A4
DB4 A3
DB3 A2
DB2 A1
DB1
DB0
C2 (1) C1 (1)
REV. B
-11-
ADF4217L/ADF4218L/ADF4219L
Table III. ADF4219L Family Latch Summary
IF REFERENCE COUNTER LATCH
THREE-STATE CPIF IF PD POLARITY IF LOCK DETECT
IF CP GAIN
IF FO
15-BIT REFERENCE COUNTER, R
CONTROL BITS
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P4 P3 P2 P5 P1 R15 R14 R13 R12 R11 R10 R9
DB9 R8
DB8 R7
DB7 R6
DB6 R5
DB5 R4
DB4 R3
DB3 R2
DB2 R1
DB1
DB0
C2 (0) C1 (0)
IF AB COUNTER LATCH
IF POWER-DOWN IF PRESCALER
13-BIT B COUNTER
5-BIT A COUNTER
CONTROL BITS
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P7 P6 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4
DB9 B3
DB8 B2
DB7 B1
DB6 A5
DB5 A4
DB4 A3
DB3 A2
DB2 A1
DB1
DB0
C2 (0) C1 (1)
RF REFERENCE COUNTER LATCH
THREE-STATE CPIF RF PD POLARITY RF LOCK DETECT RF CP GAIN
RF FO
15-BIT REFERENCE COUNTER, R
CONTROL BITS
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P12 P11 P10 P13 P9 R15 R14 R13 R12 R11 R10 R9
DB9 R8
DB8 R7
DB7 R6
DB6 R5
DB5 R4
DB4 R3
DB3 R2
DB2 R1
DB1
DB0
C2 (1) C1 (0)
RF AB COUNTER LATCH
RF POWER-DOWN RF PRESCALER
13-BIT B COUNTER
5-BIT A COUNTER
CONTROL BITS
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P16 P14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4
DB9 B3
DB8 B2
DB7 B1
DB6 A5
DB5 A4
DB4 A3
DB3 A2
DB2 A1
DB1
DB0
C2 (1) C1 (1)
-12-
REV. B
ADF4217L/ADF4218L/ADF4219L
Table IV. ADF4217L/ADF4218L/ADF4219L IF Reference Counter Latch Map
IF REFERENCE COUNTER LATCH
THREE-STATE CPIF IF PD POLARITY ADF4219L ONLY IF LOCK DETECT
IF CP GAIN
IF FO
14-BIT REFERENCE COUNTER, R
CONTROL BITS
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P4 P3 P2 P5 P1 R15 R14 R13 R12 R11 R10 R9
DB9 R8
DB8 R7
DB7 R6
DB6 R5
DB5 R4
DB4 R3
DB3 R2
DB2 R1
DB1
DB0
C2 (0) C1 (0)
R15 0 0 0 0 . . . 0 0 0 0 . P1 0 1 PD POLARITY NEGATIVE POSITIVE 1
R14 0 0 0 0 . . . 1 1 1 1 . 1
R13 0 0 0 0 . . . 1 1 1 1 . 1
R12 0 0 0 0 . . . 1 1 1 1 . 1
.......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ..........
R3 0 0 0 1 . . . 1 1 1 1 . 1
R2 0 1 1 0 . . . 0 0 1 1 . 1
R1 1 0 1 0 . . . 0 1 0 1 . 1
DIVIDE RATIO 1 2 3 4 . . . 16380 16381 16382 16383 . 32767
P5 0 1
ICP 1.0mA 4.0mA
P2 0 1
CHARGE PUMP OUTPUT NORMAL THREE-STATE
P12 P11 FROM RF R LATCH 0 0 0 0 0 0 1 1 1 1 1 1 0 0 X X 1 1 X X 0 0 1 1
P4 0 0 1 1 0 0 0 0 1 1 1 1
P3 0 1 0 1 0 1 0 1 0 1 0 1
MUXOUT LOGIC LOW STATE IF ANALOG LOCK DETECT IF REFERENCE DIVIDER OUTPUT IF N DIVIDER OUTPUT RF ANALOG LOCK DETECT RF/IF ANALOG LOCK DETECT RF REFERENCE DIVIDER RF N DIVIDER FAST LOCK OUTPUT SWITCH ON AND CONNECTED TO MUXOUT IF COUNTER RESET RF COUNTER RESET IF AND RF COUNTER RESET
REV. B
-13-
ADF4217L/ADF4218L/ADF4219L
Table V. ADF4217L/ADF4218L IF AB Counter Latch
IF AB COUNTER LATCH
IF POWER-DOWN IF PRESCALER
11-BIT B COUNTER
6-BIT A COUNTER
CONTROL BITS
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P7 P6 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2
DB9 B1
DB8
DB7 A6
DB6 A5
DB5 A4
DB4 A3
DB3 A2
DB2 A1
DB1
DB0
C2 (0) C1 (1)
A6 0 0 0 0 . . . 1 1
A5 0 0 0 0 . . . 1 1
A4 0 0 0 0 . . . 1 1
A3 0 0 0 0 . . . 1 1
A2 0 0 1 1 . . . 1 1
A1 0 1 0 1 . . . 0 1
A COUNTER DIVIDE RATIO 0 1 2 3 . . . 62 63
B11 0 0 0 . . . 1 1 1 1
B10 0 0 0 . . . 1 1 1 1
B9 0 0 0 . . . 1 1 1 1
.......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ..........
B3 0 0 0 . . . 1 1 1 1
B2 0 1 1 . . . 0 0 1 1
B1 1 0 1 . . . 0 1 0 1
B COUNTER DIVIDE RATIO NOT ALLOWED NOT ALLOWED 3 . . . 2044 2045 2046 2047
P6 0 1
IF PRESCALER 8/9 16/17
P7 0 1
IF SECTION NORMAL OPERATION POWER-DOWN
N = BP + A, P IS PRESCALER VALUE SET BY P6. B MUST BE GREATER THAN OR EQUAL TO A. TO ENSURE CONTINUOUSLY ADJACENT VALUES OF N, NMIN IS (P2 - P).
-14-
REV. B
ADF4217L/ADF4218L/ADF4219L
Table VI. ADF4219L IF AB Counter Latch
IF AB COUNTER LATCH
IF POWER-DOWN IF PRESCALER
13-BIT B COUNTER
5-BIT A COUNTER
CONTROL BITS
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P7 P6 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4
DB9 B3
DB8 B2
DB7 B1
DB6 A5
DB5 A4
DB4 A3
DB3 A2
DB2 A1
DB1
DB0
C2 (0) C1 (1)
A5 0 0 0 0 . 1 1
A4 0 0 0 0 . 1 1
A3 0 0 0 0 . 1 1
A2 0 0 1 1 . 1 1
A1 0 1 0 1 . 0 1
A COUNTER DIVIDE RATIO 0 1 2 3 . 30 31
B13 0 0 0 . . . 1 1 1 1
B12 0 0 0 . . . 1 1 1 1
B11 0 0 0 . . . 1 1 1 1
.......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ..........
B3 0 0 0 . . . 1 1 1 1
B2 0 1 1 . . . 0 0 1 1
B1 1 0 1 . . . 0 1 0 1
B COUNTER DIVIDE RATIO NOT ALLOWED NOT ALLOWED 3 . . . 8188 8189 8190 8191
P6 0 1
IF PRESCALER 8/9 16/17
P7 0 1
IF SECTION NORMAL OPERATION POWER-DOWN
N = BP + A, P IS PRESCALER VALUE SET BY P6. B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTIGUOUS VALUES OF N, NMIN IS (P2- P).
REV. B
-15-
ADF4217L/ADF4218L/ADF4219L
Table VII. RF Reference Counter Latch Map
RF REFERENCE COUNTER LATCH
THREE-STATE CPIF RF PD POLARITY ADF4129L ONLY RF LOCK DETECT RF CP GAIN
RF FO
14-BIT REFERENCE COUNTER, R
CONTROL BITS
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P12 P11 P10 P13 P9 R15 R14 R13 R12 R11 R10 R9
DB9 R8
DB8 R7
DB7 R6
DB6 R5
DB5 R4
DB4 R3
DB3 R2
DB2 R1
DB1
DB0
C2 (1) C1 (0)
R15 0 0 0 0 . . . 0 0 0 0 P9 0 1 PD POLARITY NEGATIVE POSITIVE . 1
R14 0 0 0 0 . . . 1 1 1 1 . 1
R13 0 0 0 0 . . . 1 1 1 1 . 1
R12 0 0 0 0 . . . 1 1 1 1 . 1
.......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ..........
R3 0 0 0 1 . . . 1 1 1 1 . 1
R2 0 1 1 0 . . . 0 0 1 1 . 1
R1 1 0 1 0 . . . 0 1 0 1 . 1
DIVIDE RATIO 1 2 3 4 . . . 16380 16381 16382 16383 . 32767
P13 0 1
ICP 1.0mA 4.0mA
P10 0 1
CHARGE PUMP OUTPUT NORMAL THREE-STATE
P12 0 0 0 0 0 0 1 1 1 1 1 1
P11 0 0 X X 1 1 X X 0 0 1 1
P4 P3 FROM RF R LATCH 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1
MUXOUT LOGIC LOW STATE IF ANALOG LOCK DETECT IF REFERENCE DIVIDER OUTPUT IF N DIVIDER OUTPUT RF ANALOG LOCK DETECT RF/IF ANALOG LOCK DETECT RF REFERENCE DIVIDER RF N DIVIDER FAST LOCK OUTPUT SWITCH ON AND CONNECTED TO MUXOUT IF COUNTER RESET RF COUNTER RESET IF AND RF COUNTER RESET
-16-
REV. B
ADF4217L/ADF4218L/ADF4219L
Table VIII. ADF4217L/ADF4218L RF AB Counter Latch Map
RF AB COUNTER LATCH
RF POWER-DOWN RF PRESCALER
11-BIT B COUNTER
6-BIT A COUNTER
CONTROL BITS
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P16 P14 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2
DB9 B1
DB8
DB7 A6
DB6 A5
DB5 A4
DB4 A3
DB3 A2
DB2 A1
DB1
DB0
C2 (1) C1 (1)
A6 0 0 0 0 . . . 1 1
A5 0 0 0 0 . . . 1 1
A4 0 0 0 0 . . . 1 1
A3 0 0 0 0 . . . 1 1
A2 0 0 1 1 . . . 1 1
A1 0 1 0 1 . . . 0 1
A COUNTER DIVIDE RATIO 0 1 2 3 . . . 62 63
B11 0 0 0 0 . . . 1 1 1 1
B10 0 0 0 0 . . . 1 1 1 1
B9 0 0 0 0 . . . 1 1 1 1
.......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ..........
B3 0 0 0 1 . . . 1 1 1 1
B2 0 1 1 0 . . . 0 0 1 1
B1 1 0 1 0 . . . 0 1 0 1
B COUNTER DIVIDE RATIO NOT ALLOWED NOT ALLOWED 3 4 . . . 2044 2045 2046 2047
P14 0 1 P16 0 1
RF PRESCALER ADF4217L 64/65 32/33
RF PRESCALER ADF4218L 32/33 64/65
RF SECTION NORMAL OPERATION POWER-DOWN
N = BP + A, P IS PRESCALER VALUE SET BY P6, B MUST BE GREATER THAN OR EQUAL TO A. TO ENSURE CONTINUOUSLY ADJACENT VALUES OF N FREF , N MIN IS (P2 - P).
REV. B
-17-
ADF4217L/ADF4218L/ADF4219L
Table IX. ADF4219L RF AB Counter Latch Map
RF AB COUNTER LATCH
RF POWER-DOWN RF PRESCALER
13-BIT B COUNTER
5-BIT A COUNTER
CONTROL BITS
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P16 P14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4
DB9 B3
DB8 B2
DB7 B1
DB6 A5
DB5 A4
DB4 A3
DB3 A2
DB2 A1
DB1
DB0
C2 (1) C1 (1)
A5 0 0 0 0 . 1 1
A4 0 0 0 0 . 1 1
A3 0 0 0 0 . 1 1
A2 0 0 1 1 . 1 1
A1 0 1 0 1 . 0 1
A COUNTER DIVIDE RATIO 0 1 2 3 . 30 31
B13 0 0 0 0 . . . 1 1 1 1
B12 0 0 0 0 . . . 1 1 1 1
B11 0 0 0 0 . . . 1 1 1 1
.......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ..........
B3 0 0 0 1 . . . 1 1 1 1
B2 0 1 1 0 . . . 0 0 1 1
B1 1 0 1 0 . . . 0 1 0 1
B COUNTER DIVIDE RATIO NOT ALLOWED NOT ALLOWED 3 4 . . . 8188 8189 8190 8191
P14 0 1
IF PRESCALER 16/17 32/33
P16 0 1
IF SECTION NORMAL OPERATION POWER-DOWN
N = BP + A, P IS PRESCALER VALUE SET BY P14. B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTIGUOUS VALUES OF N, NMIN IS (P2-P). A MUST BE LESS THAN P.
-18-
REV. B
ADF4217L/ADF4218L/ADF4219L
PROGRAM MODES
Table IV and Table VII show how to set up the program modes in the ADF4217L family. The following should be noted: 1. IF and RF Analog Lock Detect indicate when the PLL is in lock. When the loop is locked, and either IF or RF Analog Lock Detect is selected, the MUXOUT pin will show a logic high with narrow low-going pulses. When the IF/RF Analog Lock Detect is chosen, the locked condition is indicated only when both IF and RF loops are locked. 2. The IF Counter Reset Mode resets the R and N counters in the IF section and also puts the IF charge pump into threestate. The RF Counter Reset Mode resets the R and N counters in the RF section and also puts the RF charge pump into three-state. The IF and RF Counter Reset Mode does both of the above. Upon removal of the reset bits, the N counter resumes counting in close alignment with the R counter (maximum error is one prescaler output cycle). 3. The Fastlock Mode uses MUXOUT to switch a second loop filter damping resistor to ground during Fastlock operation. Activation of Fastlock occurs whenever RF CP Gain in the RF Reference counter is set to 1.
POWER-DOWN
The REFIN oscillator circuit is only disabled if both the IF and RF Power-Downs are set. The input register and latches remain active and are capable of loading and latching data during all the power-down modes. The IF/RF section of the devices will return to normal powered-up operation immediately upon LE latching a "0" to the appropriate power-down bit.
IF SECTION Programmable IF Reference (R) Counter
If control bits C2, C1 are 0, 0, then the data is transferred from the input shift register to the 14-bit IF R counter. Table IV shows the input shift register data format for the IF R counter and the possible divide ratios.
IF Phase Detector Polarity
P1 sets the IF Phase Detector Polarity. When the IF VCO characteristics are positive, this should be set to "1." When they are negative, it should be set to "0." See Table IV.
IF Charge Pump Three-State
P2 puts the IF charge pump into three-state mode when programmed to a "1." It should be set to "0" for normal operation. See Table IV.
IF Charge Pump Currents
It is possible to program the ADF4217L family for either synchronous or asynchronous power-down on either the IF or RF side.
Synchronous IF Power-Down
P5 sets the IF Charge Pump current. With P5 set to "0," ICP is 1.0 mA. With P5 set to "1," ICP is 4.0 mA. See Table IV.
Programmable IF AB Counter
Programming a "1" to P7 of the ADF4217L family will initiate a power-down. If P2 of the ADF4217L family has been set to "0" (normal operation), then a synchronous power-down is conducted. The device will automatically put the charge pump into threestate and then complete the power-down.
Asynchronous IF Power-Down
If control bits C2, C1 are 0, 1, the data in the input register is used to program the IF AB counter. For the ADF4217L/ADF4218L, the AB counter consists of a 6-bit swallow counter (A counter) and 11-bit programmable counter (B counter). Table V shows the input register data format for programming the IF AB counter and the possible divide ratios. The ADF4219L N counter consists of an 13-bit B counter and 5-bit A counter. Table VI shows the input register data format for programming the ADF4219L.
IF Prescaler Value
If P2 of the ADF4217L family has been set to "1" (three-state the IF charge pump), and P7 is subsequently set to "1," an asynchronous power-down is conducted. The device will go into power-down on the rising edge of LE, which latches the "1" to the IF PowerDown Bit (P7).
Synchronous RF Power-Down
P6 in the IF AB Counter Latch sets the IF prescaler value. For the ADF4217L family, 8/9 or 16/17 prescalers are available. See Table V and Table VI.
IF Power-Down
Programming a "1" to P16 of the ADF4217L family will initiate a power-down. If P10 of the ADF4217L family has been set to "0" (normal operation), a synchronous power-down is conducted. The device will automatically put the charge pump into three-state and then complete the power-down.
Asynchronous RF Power-Down
Tables IV, V, and VI show the power-down bits in the ADF4217L family. See Power-Down section for functional description.
RF SECTION Programmable RF Reference (R) Counter
If P10 of the ADF4217L family has been set to "1" (three-state the RF charge pump) and P16 is subsequently set to "1," an asynchronous power-down is conducted. The device will go into power-down on the rising edge of LE, which latches the "1" to the RF Power-Down Bit (P16). Activation of either synchronous or asynchronous power-down forces the IF/RF loop's R and N dividers to their load state conditions, and the IF/RF input section is debiased to a high impedance state.
If control bits C2, C1 are 1, 0, the data is transferred from the input shift register to the 14-bit RF R counter. Table VII shows the input shift register data format for the RF R counter and the possible divide ratios.
RF Phase Detector Polarity
P9 sets the RF Phase Detector Polarity. When the RF VCO characteristics are positive, this should be set to "1." When they are negative, it should be set to "0." See Table VII.
RF Charge Pump Three-State
P10 puts the RF charge pump into three-state mode when programmed to a "1." It should be set to "0" for normal operation. See Table VII.
REV. B
-19-
ADF4217L/ADF4218L/ADF4219L
RF Program Modes
Table IV and Table VII show how to set up the RF program modes.
RF Charge Pump Currents
program the new frequency and to initiate Fastlock. To come out of Fastlock, the RF CP Gain Bit should be returned to "0" and the extra damping resistor switched out.
APPLICATIONS SECTION Local Oscillator for GSM Handset Receiver
P13 sets the RF Charge Pump current. With P13 set to "0," ICP is 1.0 mA. With P13 set to "1," ICP is 4.0 mA. See Table VII.
Programmable RF AB Counter
If control bits C2, C1 are 1, 1, the data in the input register is used to program the RF AB counter. For the ADF4217L/ADF4218L, the AB counter consists of a 6-bit swallow counter (A counter) and 11-bit programmable counter (B counter). Table VIII shows the input register data format for programming the RF AB counter and the possible divide ratios. The ADF4219L N counter consists of a 13-bit B counter and 5-bit A counter. Table IX shows the input register data format for programming the ADF4219L.
RF Prescaler Value
The diagram in Figure 7 shows the ADF4217L/ADF4218L/ ADF4219L being used in a classic superheterodyne receiver to provide the required LOs (Local Oscillators). In this circuit, the reference input signal is applied to the circuit at FREFIN and is being generated by a 13 MHz temperature controlled crystal oscillator. In order to have a channel spacing of 200 kHz (the GSM standard), the reference input must be divided by 65, using the on-chip reference counter. The RF output frequency range is 1050 MHz to 1085 MHz. Loop filter component values are chosen so that the loop bandwidth is 20 kHz. The synthesizer is set up for a charge pump current of 4.0 mA, and the VCO sensitivity is 15.6 MHz/V. The IF output is fixed at 125 MHz. The IF loop bandwidth is chosen to be 20 kHz with a channel spacing of 200 kHz. Loop filter component values are chosen accordingly.
Local Oscillator for WCDMA Receiver
P14 in the RF AB Counter Latch sets the RF prescaler value. For the ADF4217L and ADF4218L family, 32/33 or 64/65 prescalers are available. See Table VIII. For the ADF4219L, the prescaler may be 16/17 or 32/33. See Table IX.
RF Power-Down
Tables VII, VIII, and IX show the power-down bits (Charge Pump Bit used for asynchronous in the ADF4217L family.) See Power-Down section for functional description.
RF Fastlock
Figure 8 shows the ADF4217L/ADF4218L/ADF4219L being used to generate the local oscillator frequencies in a Wideband CDMA (WCDMA) system. The RF output range needed is 1720 MHz to 1780 MHz. The VCO190-1750T from Varil-L will accomplish that. Channel spacing is 200 kHz. The Loop Bandwidth of the loop filter is 20 kHz. The VCO sensitivity is 32 MHz/V. A charge pump current of 4.0 mA is used and the desired phase margin for the loop is 45 degrees. The IF output is fixed at 200 MHz. The VCO190-200T is used. It has a sensitivity of 11.5 MHz/V. Channel spacing and loop bandwidth are chosen the same as the RF side.
RFOUT
The RF CP Gain Bit (P13) of the RF N Register in the ADF4217L family is the Fastlock Enable Bit. The loop filter should be designed for the lower current setting. When Fastlock is enabled, the RF CP current is set to maximum value. Also, an extra loop filter damping resistor to ground is switched in using the MUXOUT pin, thus compensating for the change of loop dynamics when in Fastlock Mode. Since the RF CP Gain Bit is contained in the RF N counter, only one write is needed to
IFOUT VP 100pF 18 18 100pF 3.3k 620pF 400pF VP2 CPIF 9k 3.9nF VDD2 VDD1 VP1 CPRF 620pF 3.3k 620pF 100pF VDD VP
100pF 18 18
VCC VCO190-125T
VCC VCO190-1068U
18
5.8k 6nF
18
ADF4217L/ ADF4218L/ ADF4219L
MUXOUT LOCK DETECT
100pF REFIN
DGNDRF AGNDRF DGNDIF AGNDIF
100pF
51
VDD
IFIN
RFIN CLK DATA LE 51 SPI COMPATIBLE SERIAL BUS
10MHz TCXO
DECOUPLING CAPACITORS (22 F/10pF) ON VDD, VP OF THE ADF4217L/ADF4218L/ADF4219L. THE TCXO AND ON V CC OF THE VCOs HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
Figure 7. Local Oscillator Design for GSM Receiver
-20-
REV. B
ADF4217L/ADF4218L/ADF4219L
IFOUT VP 100pF 18 18 100pF 3.3k 450pF 2.4pF VP2 CPIF 1.5k 24nF VDD2 VDD1 VP1 CPRF 760pF 3.3k 690pF 100pF VDD VP 100pF 18 18 RFOUT
VCC VCO190-200T
VCC VCO190-1750T
18
4.7k 7.5nF
18
ADF4217L/ ADF4218L/ ADF4219L
MUXOUT LOCK DETECT
100pF IFIN 51 10MHz TCXO REFIN RFIN
100pF
DGNDRF AGNDRF DGNDIF AGNDIF
CLK DATA LE
51 SPI COMPATIBLE SERIAL BUS
DECOUPLING CAPACITORS (22 F/10pF) ON VDD , VP OF THE ADF4217L/ADF4218L/ADF4219L. THE TCXO, AND ON V CC OF THE VCOs HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
Figure 8. Local Oscillator Design for WCDMA System
In this circuit, the reference input signal is applied to the circuit at REFIN by a 10 MHz TCXO (Temperature Controlled Crystal Oscillator).
INTERFACING
SCLK MOSI
CLK DATA LE ADF4217L/
ADuC812
I/O PORTS
ADF4218L/ ADF4219L
MUXOUT (LOCK DETECT)
The ADF4217L/ADF4218L/ADF4219L family has a simple SPI-compatible serial interface for writing to the device. SCLK, SDATA, and LE control the data transfer. When LE (Latch Enable) goes high, the 22 bits that have been clocked into the input register on each rising edge of SCLK will get transferred to the appropriate latch. See Figure 1 for the timing diagram and Table I for the latch truth table. The maximum allowable serial clock rate is 20 MHz. This means that the maximum update rate possible for the device is 909 kHz or one update every 1.1 microseconds. This is certainly more than adequate for systems that will have typical lock times in hundreds of microseconds.
ADuC812 Interface
Figure 9. ADuC812 to ADF421xL Interface
ADSP2181 Interface
Figure 9 shows the interface to the ADuC812 microconverter. Since the ADuC812 is based on an 8051 core, this interface can be used with any 8051-based microcontroller. The microconverter is set up for SPI Master Mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF421xL family needs a 22-bit word. This is accomplished by writing three 8-bit bytes from the microconverter to the device. When the third byte has been written the LE input should be brought high to complete the transfer. On first applying power to the ADF4217L family, it needs four writes (one each to the R counter latch and the AB counter latch for both RF1 and RF2 side) for the output to become active. When operating in the mode described, the maximum SCLOCK rate of the ADuC812 is 4 MHz. This means that the maximum rate at which the output frequency can be changed will be about 180 kHz.
Figure 10 shows the interface between the ADF4217L family and the ADSP-21xx Digital Signal Processor. As previously discussed, the ADF4217L family needs a 22-bit serial word for each latch write. The easiest way to accomplish this using the ADSP-21xx family is to use the Autobuffered Transmit Mode of Operation with Alternate Framing. This provides a means for transmitting an entire block of serial data before an interrupt is generated. Set up the word length for 8 bits and use three memory locations for each 22-bit word. To program each 22-bit latch, store the three 8-bit bytes, enable the Autobuffered Mode and then write to the transmit register of the DSP. This last operation initiates the autobuffer transfer.
SCLK DT TFS CLK DATA LE ADF4217L/
ADSP-21xx
I/O FLAG
ADF4218L/ ADF4219L
MUXOUT (LOCK DETECT)
Figure 10. ADSP-21xx to ADF421xL Interface
REV. B
-21-
ADF4217L/ADF4218L/ADF4219L
OUTLINE DIMENSIONS 20-Lead Thin Shrink SO Package [TSSOP] (RU-20)
Dimensions shown in millimeters
6.60 6.50 6.40
20
11
4.50 4.40 4.30
1 10
6.40 BSC
PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 1.20 MAX
0.20 0.09 8 0
SEATING PLANE
0.75 0.60 0.45
COMPLIANT TO JEDEC STANDARDS MO-153AC
24-Lead Chip Scale Package CASON [CSP] (CC-24)
Dimensions shown in millimeters
SEATING PLANE 1.14 1.04 0.94
4.50 BSC
VIEW A 3.50 BSC
PIN 1 INDEX AREA
TOP VIEW
0.50 BSC TYP
1.09 0.89
0.05 MAX
0.10 TYP 1 24 0.45 TYP
0.25 TYP BOTTOM VIEW
VIEW A
DIMENSIONS PER JEDEC STANDARDS MO-208, ECEA-1
-22-
REV. B
ADF4217L/ADF4218L/ADF4219L Revision History
Location 7/02--Data Sheet changed from REV. A to REV. B. Page
Change to ADF4219L SENSITIVITY SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
6/02--Data Sheet changed from REV. 0 to REV. A.
Changes to FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Changes to CASON package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
REV. B
-23-
-24-
C02655-0-7/02(B)
PRINTED IN U.S.A.

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